`timescale 1ns/1ns
`define DLY 0
`define DLY1 0
`define DLY2 0
module	divclk3(
	clk_in,
	rst_in,
	clk_out
);
input	clk_in;
input	rst_in;
output	clk_out;
reg	clk_out;

reg	clk_n;
reg	clk_not;
reg	d1;
reg	d2;
reg	clk_s;

always @(posedge clk_in or negedge rst_in)begin
	if(~rst_in)
		d1 <= #`DLY 1'b0;
	else
		d1 <= #`DLY clk_not;
end

always @(posedge clk_n or negedge rst_in)begin
	if(~rst_in)
		d2 <= #`DLY 1'b0;
	else
		d2 <= #`DLY d1;
end

always @(posedge clk_s or negedge rst_in)begin
	if(~rst_in)
		clk_out <= #`DLY 1'b0;
	else
		clk_out <= #`DLY d2;
end

always @(clk_out)
	clk_not <= #`DLY1 ~clk_out;

always @(clk_in)
	clk_n <= #`DLY1 ~clk_in;

always @(clk_out or clk_in or clk_n)begin
	if(clk_out)
		clk_s <= #`DLY2 clk_in;
	else
		clk_s <= #`DLY2 clk_n;
end

endmodule

